Ieee Research Papers Computer Architecture

Accepted and presented papers would be published into IEEE conference proceedings, which would be included in IEEE Xplore, abstracting in Ei compendex, scopus, etc.

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In order for a paper to be chosen as a top pick, it must first have been accepted in a major computer architecture conference that year.

Out of 123 top pick submissions in 2018, 12 were selected as Top Picks and 11 were selected as Honorable Mentions. student, Aniruddh Ramrakhyani, and Paul Gratz, an ECE associate professor at Texas A&M University.

Gratz’s paper titled “Synchronized Progress in Interconnection Networks (SPIN) : A New Theory for Deadlock Freedom” was selected for The IEEE Micro Top Picks in Architecture for 2018.

This issue collects the year’s most significant research papers in computer architecture based on novelty and potential for long-term impact. Gratz’s paper here: “IEEE Micro Top Paper Pick 2018 – Gratz Synchronized Progress in Interconnection Networks (SPIN) A New Theory for Deadlock Freedom”.

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Ieee Research Papers Computer Architecture

ISCA’18 is very proud and honored to host this year’s Turing Lecture, to be given by award winners John L. They demonstrate that enabling every packet to move forward at exactly the same time can help them all move forward and get out of the deadlock.Imagine the same traffic jam as before, but every car in the jam agreeing to move forward at exactly the same time to avoid any collisions. Machine Learning (ML) and Artificial Intelligence (AI) are becoming ubiquitous.A key challenge in designing the interconnection network connecting these processors is that of “deadlocks”.A deadlock is a scenario where a set of packets is stuck indefinitely and cannot move forward because they form a cyclic dependence. IEEE Micro publishes its yearly “Micro’s Top Picks from the Computer Architecture Conferences” as its May / June 2019 issue. This paper proposes a new theoretical approach to deadlock freedom in interconnection networks, based upon reframing the problem as one of coordination among independent actors as opposed to a problem of resource acquisition ordering. Gratz’s research, see Rachel Rose’s ECE article on the department news page in February 2019.This was the first work to show a deadlock-free interconnection network with fully adaptive routing, without any routing restrictions, with only a single queue at every router port. Deep Neural Networks (DNN) have demonstrated highly promising results across applications like computer vision, speech recognition, language translation, recommendation systems, and games.Honorable Mention Krishna’s paper that was selected as an Honorable Mention is entitled “MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects.” The paper was published at the 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), held March 24-28, 2018 in Williamsburg, Virginia. The computational complexity of DNNs and a need for high energy-efficiency has led to a surge in research on hardware accelerators.An analogy is that of a traffic jam in road networks where each car waits for the car in front of it to move, but no car can move if they end up forming a cycle.The traditional approaches to avoid deadlocks either restricts routes (leading to lower performance) or adds more queues (leading to more area and power).


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